1. Field of the Disclosure
This disclosure relates generally to non-volatile memories (NVMs), and more specifically, to NVMs that include adaptive write operations.
2. Description of the Related Art
Typical non-volatile memories (NVMs) tend to become more difficult to perform write operations such as program and erase due to charge trapping as the number of program/erase cycles increases. The slow down in writing may become significant and results in reduced performance of the system of which it is a part. This can be significant in any portion of the write process including soft programming where over erase places some bit cells in a high leakage condition. Soft programming then is used to slightly increase the threshold voltage to remove those NVM cells from their high leakage condition. Even though the tunneling portion of the write is normal for erase, it can be used for programming also. In any event, the write speed, whether regular programming, erasing, or soft programming, can be negatively impacted by the charge trapping. Each write operation, including each of the regular program, erase and soft program operations, typically ramps up the magnitude of the relevant high voltage pulses at a rate that is a tradeoff between write performance and the reliability of the bit cells. The current write operations are struggling to maintain the rate of scaling that is occurring for other aspects of semiconductor technology. As the technology and feature size of the memory cells become smaller and operating temperatures increase, write times are a challenge which must be managed.
Thus there is a need for write operations that improve upon one or more the issues raised above.